The present invention relates generally to integrated circuit fabrication, and more particularly to electrical contacts to capacitors which incorporate high dielectric constant materials.
A memory cell in an integrated circuit, such as a dynamic random access memory (DRAM) array, typically comprises a charge storage capacitor (or cell capacitor) coupled to an access device such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The MOSFET functions to apply or remove charge on the capacitor, thus effecting a logical state defined by the stored charge. The amount of charge stored on the capacitor is proportional to the capacitance C, defined by C=kk0A/d, where k is the dielectric constant of the capacitor dielectric, k0 is the vacuum permittivity, A is the electrode surface area and d is the distance between electrodes.
The footprint allotted to memory cells is continually being reduced as integrated circuits are scaled down in pursuit of faster processing speeds and lower power consumption. Fabrication costs per unit of memory can also be reduced by increasing packing density, as more cells (each representing a bit of memory) can be simultaneously fabricated on a single wafer. As the packing density of memory cells continues to increase, each capacitor must maintain a certain minimum charge storage to ensure reliable operation of the memory cell. It is thus increasingly important that capacitors achieve a high stored charge per footprint or unit of chip area occupied.
Several techniques have recently been developed to increase the total charge capacity of the cell capacitor without significantly affecting the chip area occupied by the cell. These techniques include increasing the effective surface area A of the capacitor electrodes by creating three-dimensional folding structures, such as trench or stacked capacitors.
Other techniques concentrate on the use of new dielectric materials and ferroelectrics having higher permittivity or dielectric constant k. Such materials include tantalum oxide (Ta2O5), barium strontium titanate (BST), strontium titanate (ST), barium titanate (BT), lead zirconium titanate (PZT), and strontium bismuth tantalate (SBT). These materials are characterized by effective dielectric constants significantly higher than conventional dielectrics (e.g., silicon oxides and nitrides). Whereas k=3.9 for silicon dioxide, in these materials, k can range from 20-40 (Ta2O5) to greater than 100, with some materials having k exceeding 300 (e.g., BST). Using such materials enables the creation of much smaller and simpler capacitor structures for a given stored charge requirement, enabling the packing density dictated by future circuit design.
However, difficulties have been encountered in incorporating the high k materials into conventional fabrication flows. For example, Ta2O5 is deposited by chemical vapor deposition (CVD) employing a highly oxidizing ambient. Furthermore, after deposition, the high k materials must be annealed to remove carbon and/or crystallize the material. This anneal is also typically conducted in the presence of a highly oxidizing ambient to ensure maintenance of the appropriate oxygen content in the dielectric. Depletion of oxygen would essentially leave metallic current leakage paths through the capacitor dielectric, leading to failure of the cell. Both the deposition and anneal may subject surrounding materials to degradation. For example, polycrystalline silicon (polysilicon) plugs beneath the high k materials are subject to oxidation.
Such oxidation is not limited to immediate surrounding materials. Rather, such oxidation may diffuse directly through an insulating layer (e.g., borophosphosilicate glass or BPSG) and degrade the polysilicon contact plug, the conductive digit/word lines, or even the silicon substrate itself. Oxidation of any of these structures reduces their conductivity and is viewed as a major obstacle to incorporating high k materials into integrated circuits. While replacing silicon with non-oxidizing materials prevents degradation of the plug itself, such materials are expensive and many tend to allow oxygen diffusion through them to other oxidizable elements.
Thus, a need exists for a memory cell structure which includes a semiconductor device, an electrical contact and a memory cell capacitor, and which reliably integrates high dielectric constant materials into the process flow.
In accordance with one aspect of the invention, an electrical contact is formed between a memory cell capacitor and the silicon substrate. The electrical contact includes a contact plug surrounded by a silicon nitride spacer. The spacer advantageously protects the contact plug and the silicon substrate from oxidizing environments, such as the environment present during subsequent processing of a high dielectric capacitor, and from other bi-directional diffusion.
In accordance with another aspect of the invention, the contact plug comprises CVD transition metals or CVD transition metal oxides. The contact plugs advantageously resist high temperatures and highly oxidizing environments, such as the environment present during fabrication of the high dielectric capacitor.
In accordance with yet another aspect of the invention, the electrical contact is formed in a process which eliminates the need for spacers along word lines. Therefore, the extra processing steps required to produce such digit line spacers may be avoided and contact footprint is effectively expanded. Therefore, the electrical contact advantageously reduces cost and complexity of the process flow while also allowing for increased density of memory cells.
Other aspects and advantages of the invention will be apparent from the detailed description below and the appended claims.